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author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 14:32:50 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 15:58:23 +0200 |
commit | b7dda723022ad00c6c0089be888eab319953faa8 (patch) | |
tree | 4fe12ce120f1809891dc4cbd862bbcdab0e90fcc /passes/opt/opt_clean.cc | |
parent | cd6574ecf652901573cbc6b89e1a59dd383ec496 (diff) | |
download | yosys-b7dda723022ad00c6c0089be888eab319953faa8.tar.gz yosys-b7dda723022ad00c6c0089be888eab319953faa8.tar.bz2 yosys-b7dda723022ad00c6c0089be888eab319953faa8.zip |
Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
Diffstat (limited to 'passes/opt/opt_clean.cc')
-rw-r--r-- | passes/opt/opt_clean.cc | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 30ab88146..fa5d8f189 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -40,7 +40,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose) SigSet<RTLIL::Cell*> wire2driver; for (auto &it : module->cells) { RTLIL::Cell *cell = it.second; - for (auto &it2 : cell->connections_) { + for (auto &it2 : cell->connections()) { if (!ct.cell_input(cell->type, it2.first)) { RTLIL::SigSpec sig = it2.second; assign_map.apply(sig); @@ -70,7 +70,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose) for (auto cell : queue) unused.erase(cell); for (auto cell : queue) { - for (auto &it : cell->connections_) { + for (auto &it : cell->connections()) { if (!ct.cell_output(cell->type, it.first)) { std::set<RTLIL::Cell*> cell_list; RTLIL::SigSpec sig = it.second; @@ -158,10 +158,10 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool for (auto &it : module->cells) { RTLIL::Cell *cell = it.second; if (ct_reg.cell_known(cell->type)) - for (auto &it2 : cell->connections_) + for (auto &it2 : cell->connections()) if (ct_reg.cell_output(cell->type, it2.first)) register_signals.add(it2.second); - for (auto &it2 : cell->connections_) + for (auto &it2 : cell->connections()) connected_signals.add(it2.second); } @@ -171,7 +171,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool for (auto &it : module->cells) { RTLIL::Cell *cell = it.second; if (ct_all.cell_known(cell->type)) - for (auto &it2 : cell->connections_) + for (auto &it2 : cell->connections()) if (ct_all.cell_output(cell->type, it2.first)) direct_sigs.insert(assign_map(it2.second)); } @@ -189,13 +189,13 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool } } - module->connections_.clear(); + module->connections().clear(); SigPool used_signals; SigPool used_signals_nodrivers; for (auto &it : module->cells) { RTLIL::Cell *cell = it.second; - for (auto &it2 : cell->connections_) { + for (auto &it2 : cell->connections()) { assign_map.apply(it2.second); used_signals.add(it2.second); if (!ct.cell_output(cell->type, it2.first)) @@ -237,7 +237,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool if (new_conn.first.size() > 0) { used_signals.add(new_conn.first); used_signals.add(new_conn.second); - module->connections_.push_back(new_conn); + module->connect(new_conn); } } } else { |