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| author | Clifford Wolf <clifford@clifford.at> | 2013-08-09 12:42:32 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-08-09 12:42:32 +0200 |
| commit | 05483619f0b776eda2f96ca7a9bfb8cdc3732a0e (patch) | |
| tree | df893fc9929cc54f684f9975834220743199d93e /passes/opt/opt_clean.cc | |
| parent | d97782b848bf5da4529e5b732b1ad06177539a93 (diff) | |
| download | yosys-05483619f0b776eda2f96ca7a9bfb8cdc3732a0e.tar.gz yosys-05483619f0b776eda2f96ca7a9bfb8cdc3732a0e.tar.bz2 yosys-05483619f0b776eda2f96ca7a9bfb8cdc3732a0e.zip | |
Some fixes to improve determinism
Diffstat (limited to 'passes/opt/opt_clean.cc')
| -rw-r--r-- | passes/opt/opt_clean.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index dbe1804ee..183d6757e 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -35,7 +35,7 @@ static int count_rm_cells, count_rm_wires; static void rmunused_module_cells(RTLIL::Module *module, bool verbose) { SigMap assign_map(module); - std::set<RTLIL::Cell*> queue, unused; + std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> queue, unused; SigSet<RTLIL::Cell*> wire2driver; for (auto &it : module->cells) { @@ -66,7 +66,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose) while (queue.size() > 0) { - std::set<RTLIL::Cell*> new_queue; + std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> new_queue; for (auto cell : queue) unused.erase(cell); for (auto cell : queue) { |