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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-23 15:44:19 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-12-23 15:44:19 +0100 |
| commit | d938ce7ab6df091e0edd40f85f08fcd5458d9d6d (patch) | |
| tree | 1e7f17e720b7ab491cfd1defebef35f07dfb5de1 /passes/memory | |
| parent | 23bb77867f56e966195d99d1d89b45d510d0b92d (diff) | |
| parent | e5eb3d2c8ace00aeedec410d17a4972a76782089 (diff) | |
| download | yosys-d938ce7ab6df091e0edd40f85f08fcd5458d9d6d.tar.gz yosys-d938ce7ab6df091e0edd40f85f08fcd5458d9d6d.tar.bz2 yosys-d938ce7ab6df091e0edd40f85f08fcd5458d9d6d.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'passes/memory')
| -rw-r--r-- | passes/memory/memory_collect.cc | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 70d98713c..369fcc84e 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -184,9 +184,6 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory) mem->parameters["\\OFFSET"] = Const(memory->start_offset); mem->parameters["\\SIZE"] = Const(memory->size); mem->parameters["\\ABITS"] = Const(addr_bits); - - while (GetSize(init_data) > 1 && init_data.bits.back() == State::Sx && init_data.bits[GetSize(init_data)-2] == State::Sx) - init_data.bits.pop_back(); mem->parameters["\\INIT"] = init_data; log_assert(sig_wr_clk.size() == wr_ports); |