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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-08 19:13:19 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-08 19:13:19 +0100 |
| commit | 7f52c18a22e85b0a2db17511b4617534395aacfb (patch) | |
| tree | b02af7b57dd707c858ca0ece3ecc6221a52c0acf /passes/memory | |
| parent | 926fa61119a64f9cf3f18de6612444d3c11534c0 (diff) | |
| download | yosys-7f52c18a22e85b0a2db17511b4617534395aacfb.tar.gz yosys-7f52c18a22e85b0a2db17511b4617534395aacfb.tar.bz2 yosys-7f52c18a22e85b0a2db17511b4617534395aacfb.zip | |
Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect
Diffstat (limited to 'passes/memory')
| -rw-r--r-- | passes/memory/memory_collect.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 40504d781..6fe5e162c 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -160,6 +160,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) sig_rd_clk_enable.optimize(); sig_rd_clk_polarity.optimize(); + sig_rd_transparent.optimize(); assert(sig_rd_clk.width == rd_ports); assert(sig_rd_clk_enable.width == rd_ports && sig_rd_clk_enable.is_fully_const()); |