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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-25 09:33:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-25 09:33:11 -0700 |
| commit | 6f36ec8ecf147f8d669f35dd616714af971db6f4 (patch) | |
| tree | 04dc0222fd51dd70edef52b733cecd2a9179c093 /passes/memory | |
| parent | d2fed0a7f1bb72ee285657b974f4996c77641a23 (diff) | |
| parent | ab6e8ce0f00bc9fcf38dc62ae9de26405f7b59d7 (diff) | |
| download | yosys-6f36ec8ecf147f8d669f35dd616714af971db6f4.tar.gz yosys-6f36ec8ecf147f8d669f35dd616714af971db6f4.tar.bz2 yosys-6f36ec8ecf147f8d669f35dd616714af971db6f4.zip | |
Merge remote-tracking branch 'origin/master' into xaig
Diffstat (limited to 'passes/memory')
| -rw-r--r-- | passes/memory/memory_dff.cc | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 220d29295..5215cce44 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -182,11 +182,17 @@ struct MemoryDffWorker if (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data)) { - bool enable_invert = mux_cells_a.count(sig_data) != 0; - Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data); - SigSpec check_q = sigmap(mux->getPort(enable_invert ? "\\B" : "\\A")); + RTLIL::SigSpec en; + RTLIL::SigSpec check_q; + + do { + bool enable_invert = mux_cells_a.count(sig_data) != 0; + Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data); + check_q = sigmap(mux->getPort(enable_invert ? "\\B" : "\\A")); + sig_data = sigmap(mux->getPort("\\Y")); + en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S")); + } while (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data)); - sig_data = sigmap(mux->getPort("\\Y")); for (auto bit : sig_data) if (sigbit_users_count[bit] > 1) goto skip_ff_after_read_merging; @@ -195,7 +201,7 @@ struct MemoryDffWorker { disconnect_dff(sig_data); cell->setPort("\\CLK", clk_data); - cell->setPort("\\EN", enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S")); + cell->setPort("\\EN", en.size() > 1 ? module->ReduceAnd(NEW_ID, en) : en); cell->setPort("\\DATA", sig_data); cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); |