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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-13 12:01:03 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-13 12:01:03 -0800 |
| commit | 52875b0d61b2b1cc83a9e9d51964a92027c3758c (patch) | |
| tree | bbcfea00583b78107498a01fe2a7cdbb48e41e2d /passes/memory | |
| parent | 9ab1feeaf11adb6b675ac4034e246cb137d07db9 (diff) | |
| parent | 1c9634558747bf5b92a309b6af013a54034c35d3 (diff) | |
| download | yosys-52875b0d61b2b1cc83a9e9d51964a92027c3758c.tar.gz yosys-52875b0d61b2b1cc83a9e9d51964a92027c3758c.tar.bz2 yosys-52875b0d61b2b1cc83a9e9d51964a92027c3758c.zip | |
Merge pull request #1533 from dh73/bram_xilinx
Adjust Xilinx xc7/xcu BRAM min bits threshold for RAMB18E1
Diffstat (limited to 'passes/memory')
0 files changed, 0 insertions, 0 deletions