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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-25 08:33:17 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-25 08:33:17 -0700 |
| commit | 42720ef6fefdf7645db47b97cd914008d68b00a9 (patch) | |
| tree | c9466cb54e8ecea134bbf60dd13c5cd878cb78fb /passes/memory | |
| parent | c4e4902098153a4ab90d383ffc00987fc06ff072 (diff) | |
| download | yosys-42720ef6fefdf7645db47b97cd914008d68b00a9.tar.gz yosys-42720ef6fefdf7645db47b97cd914008d68b00a9.tar.bz2 yosys-42720ef6fefdf7645db47b97cd914008d68b00a9.zip | |
Fix spacing
Diffstat (limited to 'passes/memory')
| -rw-r--r-- | passes/memory/memory_dff.cc | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 91ae38fa3..5215cce44 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -193,10 +193,9 @@ struct MemoryDffWorker en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S")); } while (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data)); - for (auto bit : sig_data) - if (sigbit_users_count[bit] > 1) { - goto skip_ff_after_read_merging; - } + for (auto bit : sig_data) + if (sigbit_users_count[bit] > 1) + goto skip_ff_after_read_merging; if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) && sig_data == check_q) { |