Added "yosys -D" feature

7 files changed, 7 insertions, 7 deletions

diff --git a/passes/memory/memory.cc b/passes/memory/memory.cc
index 4e74d1a48..e3c627607 100644
--- a/passes/memory/memory.cc
+++ b/passes/memory/memory.cc
@@ -53,7 +53,7 @@ struct MemoryPass : public Pass {
 		bool flag_nordff = false;
 		string memory_bram_opts;
 
-		log_header("Executing MEMORY pass.\n");
+		log_header(design, "Executing MEMORY pass.\n");
 		log_push();
 
 		size_t argidx;
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index f2d9b5847..cd424fd68 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -1211,7 +1211,7 @@ struct MemoryBramPass : public Pass {
 	{
 		rules_t rules;
 
-		log_header("Executing MEMORY_BRAM pass (mapping $mem cells to block memories).\n");
+		log_header(design, "Executing MEMORY_BRAM pass (mapping $mem cells to block memories).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index 5c0acb3e5..e068ef905 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -247,7 +247,7 @@ struct MemoryCollectPass : public Pass {
 		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
-		log_header("Executing MEMORY_COLLECT pass (generating $mem cells).\n");
+		log_header(design, "Executing MEMORY_COLLECT pass (generating $mem cells).\n");
 		extra_args(args, 1, design);
 		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second))
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index beb2016a9..40691d160 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -283,7 +283,7 @@ struct MemoryDffPass : public Pass {
 	{
 		bool flag_wr_only = false;
 
-		log_header("Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).\n");
+		log_header(design, "Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index 0b8ccb363..bffeec857 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -363,7 +363,7 @@ struct MemoryMapPass : public Pass {
 		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
-		log_header("Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n");
+		log_header(design, "Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n");
 		extra_args(args, 1, design);
 		for (auto mod : design->selected_modules())
 			MemoryMapWorker(design, mod);
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index 844f4296f..f298169de 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -747,7 +747,7 @@ struct MemorySharePass : public Pass {
 		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
-		log_header("Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n");
+		log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n");
 		extra_args(args, 1, design);
 		for (auto module : design->selected_modules())
 			MemoryShareWorker(design, module);
diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc
index 60724da77..a0fc31b5e 100644
--- a/passes/memory/memory_unpack.cc
+++ b/passes/memory/memory_unpack.cc
@@ -138,7 +138,7 @@ struct MemoryUnpackPass : public Pass {
 		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
-		log_header("Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n");
+		log_header(design, "Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n");
 		extra_args(args, 1, design);
 		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second))