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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:00:30 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:00:30 +0200 |
| commit | a84cb0493566f8f5eb610c6d7b67dda85b0f227b (patch) | |
| tree | e4b1c2f97db2c317f8b986635141dfd7bb8e78d8 /passes/memory/memory_unpack.cc | |
| parent | cd6574ecf652901573cbc6b89e1a59dd383ec496 (diff) | |
| parent | f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 (diff) | |
| download | yosys-a84cb0493566f8f5eb610c6d7b67dda85b0f227b.tar.gz yosys-a84cb0493566f8f5eb610c6d7b67dda85b0f227b.tar.bz2 yosys-a84cb0493566f8f5eb610c6d7b67dda85b0f227b.zip | |
Merge automatic and manual code changes for new cell connections API
Diffstat (limited to 'passes/memory/memory_unpack.cc')
| -rw-r--r-- | passes/memory/memory_unpack.cc | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index 9c457ad5d..f08350768 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -54,9 +54,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const(); cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_POLARITY")).extract(i, 1).as_const(); cell->parameters["\\TRANSPARENT"] = RTLIL::SigSpec(memory->parameters.at("\\RD_TRANSPARENT")).extract(i, 1).as_const(); - cell->connections_["\\CLK"] = memory->connections_.at("\\RD_CLK").extract(i, 1); - cell->connections_["\\ADDR"] = memory->connections_.at("\\RD_ADDR").extract(i*abits, abits); - cell->connections_["\\DATA"] = memory->connections_.at("\\RD_DATA").extract(i*mem->width, mem->width); + cell->set("\\CLK", memory->get("\\RD_CLK").extract(i, 1)); + cell->set("\\ADDR", memory->get("\\RD_ADDR").extract(i*abits, abits)); + cell->set("\\DATA", memory->get("\\RD_DATA").extract(i*mem->width, mem->width)); } for (int i = 0; i < num_wr_ports; i++) @@ -68,10 +68,10 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const(); cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_POLARITY")).extract(i, 1).as_const(); cell->parameters["\\PRIORITY"] = i; - cell->connections_["\\CLK"] = memory->connections_.at("\\WR_CLK").extract(i, 1); - cell->connections_["\\EN"] = memory->connections_.at("\\WR_EN").extract(i*mem->width, mem->width); - cell->connections_["\\ADDR"] = memory->connections_.at("\\WR_ADDR").extract(i*abits, abits); - cell->connections_["\\DATA"] = memory->connections_.at("\\WR_DATA").extract(i*mem->width, mem->width); + cell->set("\\CLK", memory->get("\\WR_CLK").extract(i, 1)); + cell->set("\\EN", memory->get("\\WR_EN").extract(i*mem->width, mem->width)); + cell->set("\\ADDR", memory->get("\\WR_ADDR").extract(i*abits, abits)); + cell->set("\\DATA", memory->get("\\WR_DATA").extract(i*mem->width, mem->width)); } module->remove(memory); |