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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-01 16:53:15 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-01 17:14:32 +0200 |
| commit | d13eb7e0999def2da03eb6ddef805145f7fd9c9a (patch) | |
| tree | d7634c448a42722357b474926056c10797f1546d /passes/memory/memory_share.cc | |
| parent | 97a17d39e2f0088e02ed8496d905528722115674 (diff) | |
| download | yosys-d13eb7e0999def2da03eb6ddef805145f7fd9c9a.tar.gz yosys-d13eb7e0999def2da03eb6ddef805145f7fd9c9a.tar.bz2 yosys-d13eb7e0999def2da03eb6ddef805145f7fd9c9a.zip | |
Added ModIndex helper class, some changes to RTLIL::Monitor
Diffstat (limited to 'passes/memory/memory_share.cc')
| -rw-r--r-- | passes/memory/memory_share.cc | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index fde6ea007..ace6eeaf1 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -735,9 +735,8 @@ struct MemorySharePass : public Pass { virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { log_header("Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules_) - if (design->selected(mod_it.second)) - MemoryShareWorker(design, mod_it.second); + for (auto module : design->selected_modules()) + MemoryShareWorker(design, module); } } MemorySharePass; |