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author | Ruben Undheim <ruben.undheim@gmail.com> | 2014-09-06 08:47:06 +0200 |
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committer | Ruben Undheim <ruben.undheim@gmail.com> | 2014-09-06 08:47:06 +0200 |
commit | 79cbf9067c07ed810b3466174278d77b9a05b46d (patch) | |
tree | b546123251d39df2ffd115fb0b8a08e57e7cf538 /passes/memory/memory_share.cc | |
parent | 01ef34c147dd3e3e3d13864f9c726727a4013207 (diff) | |
download | yosys-79cbf9067c07ed810b3466174278d77b9a05b46d.tar.gz yosys-79cbf9067c07ed810b3466174278d77b9a05b46d.tar.bz2 yosys-79cbf9067c07ed810b3466174278d77b9a05b46d.zip |
Corrected spelling mistakes found by lintian
Diffstat (limited to 'passes/memory/memory_share.cc')
-rw-r--r-- | passes/memory/memory_share.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index ace6eeaf1..3ae0cd2c7 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -720,7 +720,7 @@ struct MemorySharePass : public Pass { log(" address, then this feedback path is converted to a write port with\n"); log(" byte/part enable signals.\n"); log("\n"); - log(" - When multiple write ports access the same adress then this is converted\n"); + log(" - When multiple write ports access the same address then this is converted\n"); log(" to a single write port with a more complex data and/or enable logic path.\n"); log("\n"); log(" - When multiple write ports are never accessed at the same time (a SAT\n"); |