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author | Sahand Kashani <sahand.kashani@gmail.com> | 2020-04-08 23:50:37 +0200 |
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committer | Sahand Kashani <sahand.kashani@gmail.com> | 2020-04-08 23:50:37 +0200 |
commit | 9edf8869c18951ec2b75f074065f073da3253244 (patch) | |
tree | 09fba95ba6d3f93ecab828c84b9ff3f74160d7b9 /passes/memory/memory_memx.cc | |
parent | 820e3d1dad4f484f9646588f79b73b21b495e3d8 (diff) | |
parent | 5f649fc19d5cef76a634572ad0a493f1d2fd6306 (diff) | |
download | yosys-9edf8869c18951ec2b75f074065f073da3253244.tar.gz yosys-9edf8869c18951ec2b75f074065f073da3253244.tar.bz2 yosys-9edf8869c18951ec2b75f074065f073da3253244.zip |
Merge branch 'master' of github.com:YosysHQ/yosys into firrtl_backend_fileinfo
Diffstat (limited to 'passes/memory/memory_memx.cc')
-rw-r--r-- | passes/memory/memory_memx.cc | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/passes/memory/memory_memx.cc b/passes/memory/memory_memx.cc index 958370164..5d5f61c7d 100644 --- a/passes/memory/memory_memx.cc +++ b/passes/memory/memory_memx.cc @@ -47,18 +47,18 @@ struct MemoryMemxPass : public Pass { vector<Cell*> mem_port_cells; for (auto cell : module->selected_cells()) - if (cell->type.in("$memrd", "$memwr")) + if (cell->type.in(ID($memrd), ID($memwr))) mem_port_cells.push_back(cell); for (auto cell : mem_port_cells) { - IdString memid = cell->getParam("\\MEMID").decode_string(); + IdString memid = cell->getParam(ID::MEMID).decode_string(); RTLIL::Memory *mem = module->memories.at(memid); int lowest_addr = mem->start_offset; int highest_addr = mem->start_offset + mem->size - 1; - SigSpec addr = cell->getPort("\\ADDR"); + SigSpec addr = cell->getPort(ID::ADDR); addr.extend_u0(32); SigSpec addr_ok = module->Nex(NEW_ID, module->ReduceXor(NEW_ID, addr), module->ReduceXor(NEW_ID, {addr, State::S1})); @@ -66,23 +66,23 @@ struct MemoryMemxPass : public Pass { addr_ok = module->LogicAnd(NEW_ID, addr_ok, module->Ge(NEW_ID, addr, lowest_addr)); addr_ok = module->LogicAnd(NEW_ID, addr_ok, module->Le(NEW_ID, addr, highest_addr)); - if (cell->type == "$memrd") + if (cell->type == ID($memrd)) { - if (cell->getParam("\\CLK_ENABLE").as_bool()) + if (cell->getParam(ID::CLK_ENABLE).as_bool()) log_error("Cell %s.%s (%s) has an enabled clock. Clocked $memrd cells are not supported by memory_memx!\n", log_id(module), log_id(cell), log_id(cell->type)); - SigSpec rdata = cell->getPort("\\DATA"); + SigSpec rdata = cell->getPort(ID::DATA); Wire *raw_rdata = module->addWire(NEW_ID, GetSize(rdata)); module->addMux(NEW_ID, SigSpec(State::Sx, GetSize(rdata)), raw_rdata, addr_ok, rdata); - cell->setPort("\\DATA", raw_rdata); + cell->setPort(ID::DATA, raw_rdata); } - if (cell->type == "$memwr") + if (cell->type == ID($memwr)) { - SigSpec en = cell->getPort("\\EN"); + SigSpec en = cell->getPort(ID::EN); en = module->And(NEW_ID, en, addr_ok.repeat(GetSize(en))); - cell->setPort("\\EN", en); + cell->setPort(ID::EN, en); } } } |