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authorwhitequark <whitequark@whitequark.org>2020-06-19 06:15:33 +0000
committerGitHub <noreply@github.com>2020-06-19 06:15:33 +0000
commitede4b10da8fdbdcff900b93c6c723516901483ff (patch)
treed949c995f56d6c07dfe7d18ca46547a3296079b6 /passes/memory/memory_map.cc
parentbcbd44c673e07c44da735ef1d7f6eb2b6c328f98 (diff)
parent60478a8e3a7b929ea7e4f4cd1b538b41ca1f34bb (diff)
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Merge pull request #2173 from whitequark/use-cxx11-final-override
Use C++11 final/override/[[noreturn]]
Diffstat (limited to 'passes/memory/memory_map.cc')
-rw-r--r--passes/memory/memory_map.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index 9d455f55b..80dd3957d 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -403,7 +403,7 @@ struct MemoryMapWorker
struct MemoryMapPass : public Pass {
MemoryMapPass() : Pass("memory_map", "translate multiport memories to basic cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -425,7 +425,7 @@ struct MemoryMapPass : public Pass {
log(" for -attr, ignore case of <value>.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool attr_icase = false;
dict<RTLIL::IdString, std::vector<RTLIL::Const>> attributes;