kernel/ff: Refactor FfData to enable FFs with async load.

- *_en is split into *_ce (clock enable) and *_aload (async load aka
  latch gate enable), so both can be present at once
- has_d is removed
- has_gclk is added (to have a clear marker for $ff)
- d_is_const and val_d leftovers are removed
- async2sync, clk2fflogic, opt_dff are updated to operate correctly on
  FFs with async load

1 files changed, 15 insertions, 7 deletions

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 21962c238..b87ecdd99 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -71,9 +71,9 @@ struct MemQueryCache
 		// port_ren is an upper bound on when we care about the value fetched
 		// from memory this cycle.
 		int ren = ezSAT::CONST_TRUE;
-		if (ff.has_en) {
-			ren = qcsat.importSigBit(ff.sig_en);
-			if (!ff.pol_en)
+		if (ff.has_ce) {
+			ren = qcsat.importSigBit(ff.sig_ce);
+			if (!ff.pol_ce)
 				ren = qcsat.ez->NOT(ren);
 		}
 		if (ff.has_srst) {
@@ -347,6 +347,10 @@ struct MemoryDffWorker
 			log("output latches are not supported.\n");
 			return;
 		}
+		if (ff.has_aload) {
+			log("output FF has async load, not supported.\n");
+			return;
+		}
 		if (ff.has_sr) {
 			// Latches and FFs with SR are not supported.
 			log("output FF has both set and reset, not supported.\n");
@@ -491,8 +495,8 @@ struct MemoryDffWorker
 		log("merging output FF to cell.\n");
 
 		merger.remove_output_ff(bits);
-		if (ff.has_en && !ff.pol_en)
-			ff.sig_en = module->LogicNot(NEW_ID, ff.sig_en);
+		if (ff.has_ce && !ff.pol_ce)
+			ff.sig_ce = module->LogicNot(NEW_ID, ff.sig_ce);
 		if (ff.has_arst && !ff.pol_arst)
 			ff.sig_arst = module->LogicNot(NEW_ID, ff.sig_arst);
 		if (ff.has_srst && !ff.pol_srst)
@@ -500,8 +504,8 @@ struct MemoryDffWorker
 		port.clk = ff.sig_clk;
 		port.clk_enable = true;
 		port.clk_polarity = ff.pol_clk;
-		if (ff.has_en)
-			port.en = ff.sig_en;
+		if (ff.has_ce)
+			port.en = ff.sig_ce;
 		else
 			port.en = State::S1;
 		if (ff.has_arst) {
@@ -551,6 +555,10 @@ struct MemoryDffWorker
 			log("address latches are not supported.\n");
 			return;
 		}
+		if (ff.has_aload) {
+			log("address FF has async load, not supported.\n");
+			return;
+		}
 		if (ff.has_sr || ff.has_arst) {
 			log("address FF has async set and/or reset, not supported.\n");
 			return;