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| author | Clifford Wolf <clifford@clifford.at> | 2015-09-24 11:37:15 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-09-24 11:37:15 +0200 |
| commit | 3501f8e3643bfb6cd13f8d6e1acb03fa6672fd27 (patch) | |
| tree | e71a9ebf9901b8d8af579d62b9f2eda9fb8d045b /passes/memory/memory_bram.cc | |
| parent | 1b8cb9940e7c586b387cb212b4d9b9dbb881d62a (diff) | |
| download | yosys-3501f8e3643bfb6cd13f8d6e1acb03fa6672fd27.tar.gz yosys-3501f8e3643bfb6cd13f8d6e1acb03fa6672fd27.tar.bz2 yosys-3501f8e3643bfb6cd13f8d6e1acb03fa6672fd27.zip | |
Fixed memory_bram for ROMs in BRAMs with write-enable inputs
Diffstat (limited to 'passes/memory/memory_bram.cc')
| -rw-r--r-- | passes/memory/memory_bram.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 824d6a6e8..f638b5bb7 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -433,7 +433,7 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram, SigSpec rd_data = cell->getPort("\\RD_DATA"); SigSpec rd_addr = cell->getPort("\\RD_ADDR"); - if (match.shuffle_enable && bram.dbits >= portinfos.at(match.shuffle_enable - 'A').enable*2 && portinfos.at(match.shuffle_enable - 'A').enable > 0) + if (match.shuffle_enable && bram.dbits >= portinfos.at(match.shuffle_enable - 'A').enable*2 && portinfos.at(match.shuffle_enable - 'A').enable > 0 && wr_ports > 0) { int bucket_size = bram.dbits / portinfos.at(match.shuffle_enable - 'A').enable; log(" Shuffle bit order to accommodate enable buckets of size %d..\n", bucket_size); |