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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-21 13:34:33 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-21 13:34:33 +0200 |
| commit | d7763634b68a735443c61aa32918ee0cdd6e9250 (patch) | |
| tree | d04a1d072d727d0776c42f68668785403cc92bf5 /passes/hierarchy | |
| parent | 721f1f5ecfb6334904f6058d6d376d21b5efc438 (diff) | |
| download | yosys-d7763634b68a735443c61aa32918ee0cdd6e9250.tar.gz yosys-d7763634b68a735443c61aa32918ee0cdd6e9250.tar.bz2 yosys-d7763634b68a735443c61aa32918ee0cdd6e9250.zip | |
After reading the SV spec, using non-standard predict() instead of expect()
Diffstat (limited to 'passes/hierarchy')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 14d67884e..92fcb7d40 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -313,7 +313,7 @@ bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod) if (cache.count(mod) == 0) for (auto c : mod->cells()) { RTLIL::Module *m = mod->design->module(c->type); - if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume", "$expect")) + if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume", "$predict")) return cache[mod] = true; } return cache[mod]; |