Renamed RTLIL::{Module,Cell}::connections to connections_

2 files changed, 11 insertions, 11 deletions

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 90f377e0d..4306c29eb 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -58,7 +58,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 		for (auto i1 : design->modules)
 		for (auto i2 : i1.second->cells)
 			if (i2.second->type == celltype) {
-				for (auto &conn : i2.second->connections) {
+				for (auto &conn : i2.second->connections_) {
 					if (conn.first[0] != '$')
 						portnames.insert(conn.first);
 					portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.size());
@@ -219,7 +219,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
 
 		RTLIL::Module *mod = design->modules[cell->type];
 
-		for (auto &conn : cell->connections) {
+		for (auto &conn : cell->connections_) {
 			int conn_size = conn.second.size();
 			std::string portname = conn.first;
 			if (portname.substr(0, 1) == "$") {
@@ -486,7 +486,7 @@ struct HierarchyPass : public Pass {
 				RTLIL::Cell *cell = cell_it.second;
 				if (design->modules.count(cell->type) == 0)
 					continue;
-				for (auto &conn : cell->connections)
+				for (auto &conn : cell->connections_)
 					if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
 						pos_mods.insert(design->modules.at(cell->type));
 						pos_work.push_back(std::pair<RTLIL::Module*,RTLIL::Cell*>(mod_it.second, cell));
@@ -507,7 +507,7 @@ struct HierarchyPass : public Pass {
 				log("Mapping positional arguments of cell %s.%s (%s).\n",
 						RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
 				std::map<RTLIL::IdString, RTLIL::SigSpec> new_connections;
-				for (auto &conn : cell->connections)
+				for (auto &conn : cell->connections_)
 					if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
 						int id = atoi(conn.first.c_str()+1);
 						std::pair<RTLIL::Module*,int> key(design->modules.at(cell->type), id);
@@ -519,7 +519,7 @@ struct HierarchyPass : public Pass {
 							new_connections[pos_map.at(key)] = conn.second;
 					} else
 						new_connections[conn.first] = conn.second;
-				cell->connections = new_connections;
+				cell->connections_ = new_connections;
 			}
 		}
 
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index be580ca04..df5fd8e37 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -79,11 +79,11 @@ struct SubmodWorker
 		wire_flags.clear();
 		for (RTLIL::Cell *cell : submod.cells) {
 			if (ct.cell_known(cell->type)) {
-				for (auto &conn : cell->connections)
+				for (auto &conn : cell->connections_)
 					flag_signal(conn.second, true, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first), false, false);
 			} else {
 				log("WARNING: Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str());
-				for (auto &conn : cell->connections)
+				for (auto &conn : cell->connections_)
 					flag_signal(conn.second, true, true, true, false, false);
 			}
 		}
@@ -92,11 +92,11 @@ struct SubmodWorker
 			if (submod.cells.count(cell) > 0)
 				continue;
 			if (ct.cell_known(cell->type)) {
-				for (auto &conn : cell->connections)
+				for (auto &conn : cell->connections_)
 					flag_signal(conn.second, false, false, false, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first));
 			} else {
 				flag_found_something = false;
-				for (auto &conn : cell->connections)
+				for (auto &conn : cell->connections_)
 					flag_signal(conn.second, false, false, false, true, true);
 				if (flag_found_something)
 					log("WARNING: Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str());
@@ -163,7 +163,7 @@ struct SubmodWorker
 
 		for (RTLIL::Cell *cell : submod.cells) {
 			RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell);
-			for (auto &conn : new_cell->connections)
+			for (auto &conn : new_cell->connections_)
 				for (auto &bit : conn.second)
 					if (bit.wire != NULL) {
 						assert(wire_flags.count(bit.wire) > 0);
@@ -180,7 +180,7 @@ struct SubmodWorker
 			RTLIL::Wire *old_wire = it.first;
 			RTLIL::Wire *new_wire = it.second.new_wire;
 			if (new_wire->port_id > 0)
-				new_cell->connections[new_wire->name] = RTLIL::SigSpec(old_wire);
+				new_cell->connections_[new_wire->name] = RTLIL::SigSpec(old_wire);
 		}
 	}