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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:51:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:51:45 +0200 |
| commit | 4c4b6021562c598c4510831bd547edaa97d14dac (patch) | |
| tree | 7d8bde9d617e67431bdb6c51b5e27ea1836fe7a5 /passes/hierarchy | |
| parent | f9946232adf887e5aa4a48c64f88eaa17e424009 (diff) | |
| download | yosys-4c4b6021562c598c4510831bd547edaa97d14dac.tar.gz yosys-4c4b6021562c598c4510831bd547edaa97d14dac.tar.bz2 yosys-4c4b6021562c598c4510831bd547edaa97d14dac.zip | |
Refactoring: Renamed RTLIL::Module::cells to cells_
Diffstat (limited to 'passes/hierarchy')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 10 | ||||
| -rw-r--r-- | passes/hierarchy/submod.cc | 6 |
2 files changed, 8 insertions, 8 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index a266c3445..550ec39f0 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -38,7 +38,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell std::set<std::string> found_celltypes; for (auto i1 : design->modules) - for (auto i2 : i1.second->cells) + for (auto i2 : i1.second->cells_) { RTLIL::Cell *cell = i2.second; if (cell->type[0] == '$' || design->modules.count(cell->type) > 0) @@ -56,7 +56,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell log("Generate module for cell type %s:\n", celltype.c_str()); for (auto i1 : design->modules) - for (auto i2 : i1.second->cells) + for (auto i2 : i1.second->cells_) if (i2.second->type == celltype) { for (auto &conn : i2.second->connections()) { if (conn.first[0] != '$') @@ -137,7 +137,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla std::map<RTLIL::Cell*, std::pair<int, int>> array_cells; std::string filename; - for (auto &cell_it : module->cells) + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; @@ -252,7 +252,7 @@ static void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*> &us log("Used module: %*s%s\n", indent, "", mod->name.c_str()); used.insert(mod); - for (auto &it : mod->cells) { + for (auto &it : mod->cells_) { if (design->modules.count(it.second->type) > 0) hierarchy_worker(design, used, design->modules[it.second->type], indent+4); } @@ -479,7 +479,7 @@ struct HierarchyPass : public Pass { std::vector<std::pair<RTLIL::Module*,RTLIL::Cell*>> pos_work; for (auto &mod_it : design->modules) - for (auto &cell_it : mod_it.second->cells) { + for (auto &cell_it : mod_it.second->cells_) { RTLIL::Cell *cell = cell_it.second; if (design->modules.count(cell->type) == 0) continue; diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 774aabae1..374102756 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -87,7 +87,7 @@ struct SubmodWorker flag_signal(conn.second, true, true, true, false, false); } } - for (auto &it : module->cells) { + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; if (submod.cells.count(cell) > 0) continue; @@ -215,7 +215,7 @@ struct SubmodWorker for (auto &it : module->wires_) it.second->attributes.erase("\\submod"); - for (auto &it : module->cells) + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; if (cell->attributes.count("\\submod") == 0 || cell->attributes["\\submod"].bits.size() == 0) { @@ -239,7 +239,7 @@ struct SubmodWorker } else { - for (auto &it : module->cells) + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; if (!design->selected(module, cell)) |