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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-20 12:45:51 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-20 16:06:48 +0200 |
| commit | 436e3c0a7cbe5a482e14857e4e5a1d02b3464ae8 (patch) | |
| tree | eb537e2edc2e2eebd2cac62b242501650ea56be3 /passes/hierarchy | |
| parent | 397dfccb304a12a40d34c4454a5cb4acee8be75f (diff) | |
| download | yosys-436e3c0a7cbe5a482e14857e4e5a1d02b3464ae8.tar.gz yosys-436e3c0a7cbe5a482e14857e4e5a1d02b3464ae8.tar.bz2 yosys-436e3c0a7cbe5a482e14857e4e5a1d02b3464ae8.zip | |
Refactor code to avoid code duplication + added comments
Diffstat (limited to 'passes/hierarchy')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 9c7dad3d3..0c782b8ab 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -255,12 +255,15 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check RTLIL::IdString interface_name = interface_name_str; bool not_found_interface = false; if(module->get_bool_attribute("\\interfaces_replaced_in_module")) { // If 'interfaces' in the cell have not be been handled yet, there is no need to derive the sub-module either + // Check if the interface instance is present in module: + // Interface instances may either have the plain name or the name appended with '_inst_from_top_dummy'. + // Check for both of them here int nexactmatch = interfaces_in_module.count(interface_name) > 0; std::string interface_name_str2 = interface_name_str + "_inst_from_top_dummy"; RTLIL::IdString interface_name2 = interface_name_str2; int nmatch2 = interfaces_in_module.count(interface_name2) > 0; - if (nexactmatch > 0 || nmatch2 > 0) { // Check if the interface instance is present in module - if (nexactmatch != 0) + if (nexactmatch > 0 || nmatch2 > 0) { + if (nexactmatch != 0) // Choose the one with the plain name if it exists interface_name2 = interface_name; RTLIL::Module *mod_replace_ports = interfaces_in_module.at(interface_name2); for (auto &mod_wire : mod_replace_ports->wires_) { // Go over all wires in interface, and add replacements to lists. |