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author | Clifford Wolf <clifford@clifford.at> | 2018-01-04 13:23:29 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2018-01-04 13:23:29 +0100 |
commit | 2d140a44ebfff31876778a4e70102763aa1cb595 (patch) | |
tree | 15139ab2e82842f8acddee0bf02a6781090345d0 /passes/hierarchy | |
parent | 9804ebedbfd7db66849874bd11b167deb1bfed18 (diff) | |
download | yosys-2d140a44ebfff31876778a4e70102763aa1cb595.tar.gz yosys-2d140a44ebfff31876778a4e70102763aa1cb595.tar.bz2 yosys-2d140a44ebfff31876778a4e70102763aa1cb595.zip |
Temporarily derive blackbox modules in hierarchy to evaluate port widths
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/hierarchy')
-rw-r--r-- | passes/hierarchy/hierarchy.cc | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index c460fbbfc..524d57854 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -620,6 +620,8 @@ struct HierarchyPass : public Pass { } } + std::set<Module*> blackbox_derivatives; + for (auto module : design->modules()) for (auto cell : module->cells()) { @@ -628,9 +630,17 @@ struct HierarchyPass : public Pass { Module *m = design->module(cell->type); - if (m == nullptr || m->get_bool_attribute("\\blackbox")) + if (m == nullptr) continue; + if (m->get_bool_attribute("\\blackbox") && cell->parameters.size()) { + IdString new_m_name = m->derive(design, cell->parameters); + if (new_m_name != m->name) { + m = design->module(new_m_name); + blackbox_derivatives.insert(m); + } + } + for (auto &conn : cell->connections()) { Wire *w = m->wire(conn.first); @@ -673,6 +683,9 @@ struct HierarchyPass : public Pass { } } + for (auto module : blackbox_derivatives) + design->remove(module); + log_pop(); } } HierarchyPass; |