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authorUdi Finkelstein <github@udifink.com>2018-09-18 01:27:01 +0300
committerUdi Finkelstein <github@udifink.com>2018-09-18 01:27:01 +0300
commitc693f595c53e2e40840ff40b5b5ba06767582d23 (patch)
treede5e3f353f3222abca7186996e88cd9d635a964b /passes/hierarchy/submod.cc
parentf6fe73b31f6e6d8966ad4ddae860b4d79133cce2 (diff)
parent592a82c0ad8beb6de023aa2a131aab6472f949e8 (diff)
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Merge branch 'master' into pr_reg_wire_error
Diffstat (limited to 'passes/hierarchy/submod.cc')
-rw-r--r--passes/hierarchy/submod.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index e9ee4eef9..ec242aa1f 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -269,7 +269,7 @@ struct SubmodWorker
struct SubmodPass : public Pass {
SubmodPass() : Pass("submod", "moving part of a module to a new submodule") { }
- virtual void help()
+ void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -297,7 +297,7 @@ struct SubmodPass : public Pass {
log("with -copy to not modify the source module.\n");
log("\n");
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
log_header(design, "Executing SUBMOD pass (moving cells to submodules as requested).\n");
log_push();