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authorAman Goel <amangoel@umich.edu>2018-08-18 08:18:40 +0530
committerGitHub <noreply@github.com>2018-08-18 08:18:40 +0530
commit61f002c908830d59e883d25668b731e7d12470d0 (patch)
tree25174f7321f60e14ca6c144544f29971c40abe9b /passes/hierarchy/submod.cc
parent5dcb899e76a82c8aa84552a59f4a9f64394e7785 (diff)
parente343f3e6d475984c21611474bffe7dcd8f599497 (diff)
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Merge pull request #3 from YosysHQ/master
Updates from official repo
Diffstat (limited to 'passes/hierarchy/submod.cc')
-rw-r--r--passes/hierarchy/submod.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index e9ee4eef9..ec242aa1f 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -269,7 +269,7 @@ struct SubmodWorker
struct SubmodPass : public Pass {
SubmodPass() : Pass("submod", "moving part of a module to a new submodule") { }
- virtual void help()
+ void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -297,7 +297,7 @@ struct SubmodPass : public Pass {
log("with -copy to not modify the source module.\n");
log("\n");
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
log_header(design, "Executing SUBMOD pass (moving cells to submodules as requested).\n");
log_push();