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| author | Clifford Wolf <clifford@clifford.at> | 2014-12-19 18:47:19 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-12-19 18:47:19 +0100 |
| commit | bacd3699b3ce75b716f8a233ca955fe188f8cbef (patch) | |
| tree | c21ce7b82669546571f1c2ffa465fffeddb88ccd /passes/hierarchy/hierarchy.cc | |
| parent | 30de490d867e4eaf9a7eb59ca85b976179b346ba (diff) | |
| download | yosys-bacd3699b3ce75b716f8a233ca955fe188f8cbef.tar.gz yosys-bacd3699b3ce75b716f8a233ca955fe188f8cbef.tar.bz2 yosys-bacd3699b3ce75b716f8a233ca955fe188f8cbef.zip | |
Checking existence of ports in "hierarchy -check"
Diffstat (limited to 'passes/hierarchy/hierarchy.cc')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index e070afdd5..028a0f0c2 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -199,6 +199,19 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check if (design->modules_.count(cell->type) == 0) log_error("File `%s' from libdir does not declare module `%s'.\n", filename.c_str(), cell->type.c_str()); did_something = true; + } else + if (flag_check) + { + RTLIL::Module *mod = design->module(cell->type); + for (auto &conn : cell->connections()) + if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') { + int id = atoi(conn.first.c_str()+1); + if (id < 0 || id >= GetSize(mod->ports)) + log_error("Module `%s' referenced in module `%s' in cell `%s' has only %d ports, requested port %d.\n", + log_id(cell->type), log_id(module), log_id(cell), GetSize(mod->ports), id + 1); + } else if (mod->wire(conn.first) == nullptr || mod->wire(conn.first)->port_id == 0) + log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a port named '%s'.\n", + log_id(cell->type), log_id(module), log_id(cell), log_id(conn.first)); } if (cell->parameters.size() == 0) |