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| author | Clifford Wolf <clifford@clifford.at> | 2017-08-21 15:02:16 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-08-21 15:02:16 +0200 |
| commit | df3e6e1ec99a409c7e3d4e381b55cee7031c009a (patch) | |
| tree | d2129e08c0b4d03b00ce71eed56af651e465e628 /passes/fsm | |
| parent | ca53fba44a8f49fc96e8f2913eb55b622ec0638a (diff) | |
| download | yosys-df3e6e1ec99a409c7e3d4e381b55cee7031c009a.tar.gz yosys-df3e6e1ec99a409c7e3d4e381b55cee7031c009a.tar.bz2 yosys-df3e6e1ec99a409c7e3d4e381b55cee7031c009a.zip | |
Remove some dead code from fsm_map
Diffstat (limited to 'passes/fsm')
| -rw-r--r-- | passes/fsm/fsm_map.cc | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index c42303752..3edaf84d2 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -274,9 +274,6 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) { RTLIL::SigSpec sig_a(RTLIL::State::Sx, next_state_wire->width); RTLIL::SigSpec sig_b, sig_s; - int reset_state = fsm_data.reset_state; - if (reset_state < 0) - reset_state = 0; for (size_t i = 0; i < fsm_data.state_table.size(); i++) { RTLIL::Const state = fsm_data.state_table[i]; |