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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-23 20:32:28 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-23 20:32:28 +0200 |
| commit | c094c53de83707a5bf1b268640283f1dde235873 (patch) | |
| tree | 27e480f63e0d34d8cbfcf8fcf29472c198381296 /passes/fsm | |
| parent | 8fd8e4a468fb650fe5dcbe892c07010f627e2c2b (diff) | |
| download | yosys-c094c53de83707a5bf1b268640283f1dde235873.tar.gz yosys-c094c53de83707a5bf1b268640283f1dde235873.tar.bz2 yosys-c094c53de83707a5bf1b268640283f1dde235873.zip | |
Removed RTLIL::SigSpec::optimize()
Diffstat (limited to 'passes/fsm')
| -rw-r--r-- | passes/fsm/fsm_map.cc | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 9dda2ba89..cee267629 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -42,13 +42,10 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const eq_sig_a.append(ctrl_in.extract(j, 1)); eq_sig_b.append(RTLIL::SigSpec(pattern.bits[j])); } - eq_sig_a.optimize(); - eq_sig_b.optimize(); for (int in_state : it.second) if (fullstate_cache.count(in_state) == 0) or_sig.append(RTLIL::SigSpec(state_onehot, in_state)); - or_sig.optimize(); if (or_sig.size() == 0) continue; @@ -218,8 +215,6 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) sig_a.append(RTLIL::SigSpec(state_wire, j)); sig_b.append(RTLIL::SigSpec(state.bits[j])); } - sig_a.optimize(); - sig_b.optimize(); if (sig_b == RTLIL::SigSpec(RTLIL::State::S1)) { |