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| author | Clifford Wolf <clifford@clifford.at> | 2017-01-26 09:19:28 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-01-26 09:19:28 +0100 |
| commit | 45e10c1c892a7f3082beb9a15aeaaada52267742 (patch) | |
| tree | 574ccd798842a7856687b3f23f6bb551c7025665 /passes/fsm | |
| parent | 49b816048833d25921e45bfb248643acbf23b8de (diff) | |
| download | yosys-45e10c1c892a7f3082beb9a15aeaaada52267742.tar.gz yosys-45e10c1c892a7f3082beb9a15aeaaada52267742.tar.bz2 yosys-45e10c1c892a7f3082beb9a15aeaaada52267742.zip | |
Be more conservative with merging large cells into FSMs
Diffstat (limited to 'passes/fsm')
| -rw-r--r-- | passes/fsm/fsm_expand.cc | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index 0a2166b99..2c344a1c1 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -54,13 +54,27 @@ struct FsmExpand if (cell->getPort("\\A").size() < 2) return true; + int in_bits = 0; RTLIL::SigSpec new_signals; - if (cell->hasPort("\\A")) + + if (cell->hasPort("\\A")) { + in_bits += GetSize(cell->getPort("\\A")); new_signals.append(assign_map(cell->getPort("\\A"))); - if (cell->hasPort("\\B")) + } + + if (cell->hasPort("\\B")) { + in_bits += GetSize(cell->getPort("\\B")); new_signals.append(assign_map(cell->getPort("\\B"))); - if (cell->hasPort("\\S")) + } + + if (cell->hasPort("\\S")) { + in_bits += GetSize(cell->getPort("\\S")); new_signals.append(assign_map(cell->getPort("\\S"))); + } + + if (in_bits > 8) + return false; + if (cell->hasPort("\\Y")) new_signals.append(assign_map(cell->getPort("\\Y"))); |