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author | Udi Finkelstein <github@udifink.com> | 2018-09-18 01:27:01 +0300 |
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committer | Udi Finkelstein <github@udifink.com> | 2018-09-18 01:27:01 +0300 |
commit | c693f595c53e2e40840ff40b5b5ba06767582d23 (patch) | |
tree | de5e3f353f3222abca7186996e88cd9d635a964b /passes/fsm/fsm_recode.cc | |
parent | f6fe73b31f6e6d8966ad4ddae860b4d79133cce2 (diff) | |
parent | 592a82c0ad8beb6de023aa2a131aab6472f949e8 (diff) | |
download | yosys-c693f595c53e2e40840ff40b5b5ba06767582d23.tar.gz yosys-c693f595c53e2e40840ff40b5b5ba06767582d23.tar.bz2 yosys-c693f595c53e2e40840ff40b5b5ba06767582d23.zip |
Merge branch 'master' into pr_reg_wire_error
Diffstat (limited to 'passes/fsm/fsm_recode.cc')
-rw-r--r-- | passes/fsm/fsm_recode.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index e1bde728f..fa1ff48cc 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -126,7 +126,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs struct FsmRecodePass : public Pass { FsmRecodePass() : Pass("fsm_recode", "recoding finite state machines") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -151,7 +151,7 @@ struct FsmRecodePass : public Pass { log(" .map <old_bitpattern> <new_bitpattern>\n"); log("\n"); } - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { FILE *fm_set_fsm_file = NULL; FILE *encfile = NULL; |