Renamed port access function on RTLIL::Cell, added param access functions

1 files changed, 24 insertions, 24 deletions

diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc
index 8b9ad6be7..99b736c1b 100644
--- a/passes/fsm/fsm_map.cc
+++ b/passes/fsm/fsm_map.cc
@@ -58,9 +58,9 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 			and_sig.append(RTLIL::SigSpec(eq_wire));
 
 			RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq");
-			eq_cell->set("\\A", eq_sig_a);
-			eq_cell->set("\\B", eq_sig_b);
-			eq_cell->set("\\Y", RTLIL::SigSpec(eq_wire));
+			eq_cell->setPort("\\A", eq_sig_a);
+			eq_cell->setPort("\\B", eq_sig_b);
+			eq_cell->setPort("\\Y", RTLIL::SigSpec(eq_wire));
 			eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
 			eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
 			eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.size());
@@ -80,8 +80,8 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 				and_sig.append(RTLIL::SigSpec(or_wire));
 
 				RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or");
-				or_cell->set("\\A", or_sig);
-				or_cell->set("\\Y", RTLIL::SigSpec(or_wire));
+				or_cell->setPort("\\A", or_sig);
+				or_cell->setPort("\\Y", RTLIL::SigSpec(or_wire));
 				or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
 				or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.size());
 				or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
@@ -96,9 +96,9 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 				cases_vector.append(RTLIL::SigSpec(and_wire));
 
 				RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$and");
-				and_cell->set("\\A", and_sig.extract(0, 1));
-				and_cell->set("\\B", and_sig.extract(1, 1));
-				and_cell->set("\\Y", RTLIL::SigSpec(and_wire));
+				and_cell->setPort("\\A", and_sig.extract(0, 1));
+				and_cell->setPort("\\B", and_sig.extract(1, 1));
+				and_cell->setPort("\\Y", RTLIL::SigSpec(and_wire));
 				and_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
 				and_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
 				and_cell->parameters["\\A_WIDTH"] = RTLIL::Const(1);
@@ -119,8 +119,8 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 
 	if (cases_vector.size() > 1) {
 		RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or");
-		or_cell->set("\\A", cases_vector);
-		or_cell->set("\\Y", output);
+		or_cell->setPort("\\A", cases_vector);
+		or_cell->setPort("\\Y", output);
 		or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
 		or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.size());
 		or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
@@ -138,8 +138,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 	FsmData fsm_data;
 	fsm_data.copy_from_cell(fsm_cell);
 
-	RTLIL::SigSpec ctrl_in = fsm_cell->get("\\CTRL_IN");
-	RTLIL::SigSpec ctrl_out = fsm_cell->get("\\CTRL_OUT");
+	RTLIL::SigSpec ctrl_in = fsm_cell->getPort("\\CTRL_IN");
+	RTLIL::SigSpec ctrl_out = fsm_cell->getPort("\\CTRL_OUT");
 
 	// create state register
 
@@ -151,7 +151,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 	RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits);
 
 	RTLIL::Cell *state_dff = module->addCell(NEW_ID, "");
-	if (fsm_cell->get("\\ARST").is_fully_const()) {
+	if (fsm_cell->getPort("\\ARST").is_fully_const()) {
 		state_dff->type = "$dff";
 	} else {
 		state_dff->type = "$adff";
@@ -160,13 +160,13 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 		for (auto &bit : state_dff->parameters["\\ARST_VALUE"].bits)
 			if (bit != RTLIL::State::S1)
 				bit = RTLIL::State::S0;
-		state_dff->set("\\ARST", fsm_cell->get("\\ARST"));
+		state_dff->setPort("\\ARST", fsm_cell->getPort("\\ARST"));
 	}
 	state_dff->parameters["\\WIDTH"] = RTLIL::Const(fsm_data.state_bits);
 	state_dff->parameters["\\CLK_POLARITY"] = fsm_cell->parameters["\\CLK_POLARITY"];
-	state_dff->set("\\CLK", fsm_cell->get("\\CLK"));
-	state_dff->set("\\D", RTLIL::SigSpec(next_state_wire));
-	state_dff->set("\\Q", RTLIL::SigSpec(state_wire));
+	state_dff->setPort("\\CLK", fsm_cell->getPort("\\CLK"));
+	state_dff->setPort("\\D", RTLIL::SigSpec(next_state_wire));
+	state_dff->setPort("\\Q", RTLIL::SigSpec(state_wire));
 
 	// decode state register
 
@@ -194,9 +194,9 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 			encoding_is_onehot = false;
 
 			RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq");
-			eq_cell->set("\\A", sig_a);
-			eq_cell->set("\\B", sig_b);
-			eq_cell->set("\\Y", RTLIL::SigSpec(state_onehot, i));
+			eq_cell->setPort("\\A", sig_a);
+			eq_cell->setPort("\\B", sig_b);
+			eq_cell->setPort("\\Y", RTLIL::SigSpec(state_onehot, i));
 			eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
 			eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
 			eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size());
@@ -260,10 +260,10 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 		}
 
 		RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$safe_pmux");
-		mux_cell->set("\\A", sig_a);
-		mux_cell->set("\\B", sig_b);
-		mux_cell->set("\\S", sig_s);
-		mux_cell->set("\\Y", RTLIL::SigSpec(next_state_wire));
+		mux_cell->setPort("\\A", sig_a);
+		mux_cell->setPort("\\B", sig_b);
+		mux_cell->setPort("\\S", sig_s);
+		mux_cell->setPort("\\Y", RTLIL::SigSpec(next_state_wire));
 		mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size());
 		mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size());
 	}