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author | Jim Lawson <ucbjrl@berkeley.edu> | 2018-08-22 08:42:34 -0700 |
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committer | GitHub <noreply@github.com> | 2018-08-22 08:42:34 -0700 |
commit | 2c0601eb6f2c5ed0d376ed880efda48a2aeeb9ef (patch) | |
tree | 02b9412c9249cce3714972c8385d66f8093bfc17 /passes/fsm/fsm_map.cc | |
parent | 8b92ddb9d2635c30636b17ff3d24bc09a44b8551 (diff) | |
parent | 408077769ff022f78f10ec1ffb60926361f8dc9f (diff) | |
download | yosys-2c0601eb6f2c5ed0d376ed880efda48a2aeeb9ef.tar.gz yosys-2c0601eb6f2c5ed0d376ed880efda48a2aeeb9ef.tar.bz2 yosys-2c0601eb6f2c5ed0d376ed880efda48a2aeeb9ef.zip |
Merge pull request #1 from YosysHQ/master
merge with YosysHQ master
Diffstat (limited to 'passes/fsm/fsm_map.cc')
-rw-r--r-- | passes/fsm/fsm_map.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 3edaf84d2..90c958912 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -322,7 +322,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) struct FsmMapPass : public Pass { FsmMapPass() : Pass("fsm_map", "mapping FSMs to basic logic") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -331,7 +331,7 @@ struct FsmMapPass : public Pass { log("This pass translates FSM cells to flip-flops and logic.\n"); log("\n"); } - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing FSM_MAP pass (mapping FSMs to basic logic).\n"); extra_args(args, 1, design); |