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author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 20:12:50 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 20:12:50 +0200 |
commit | 946ddff9cef3ea0b4dad8664319fb13074133775 (patch) | |
tree | e35f5ebe3cd76a8e10fe945872e32c2ed3a7d815 /passes/fsm/fsm_extract.cc | |
parent | d49dec1f861ce11a87c48cc21c8edc1755802a5f (diff) | |
download | yosys-946ddff9cef3ea0b4dad8664319fb13074133775.tar.gz yosys-946ddff9cef3ea0b4dad8664319fb13074133775.tar.bz2 yosys-946ddff9cef3ea0b4dad8664319fb13074133775.zip |
Changed a lot of code to the new RTLIL::Wire constructors
Diffstat (limited to 'passes/fsm/fsm_extract.cc')
-rw-r--r-- | passes/fsm/fsm_extract.cc | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index ff3ac7608..51a4a75e7 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -296,10 +296,7 @@ static void extract_fsm(RTLIL::Wire *wire) RTLIL::Cell *cell = module->cells.at(cellport.first); RTLIL::SigSpec port_sig = assign_map(cell->get(cellport.second)); RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out); - RTLIL::Wire *unconn_wire = new RTLIL::Wire; - unconn_wire->name = stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++); - unconn_wire->width = unconn_sig.size(); - module->wires[unconn_wire->name] = unconn_wire; + RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++), unconn_sig.size()); port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]); } } |