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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-25 15:05:18 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-25 17:56:19 +0200 |
| commit | 2bec47a4045d23d46e7d300cbf80b2dce1a549a9 (patch) | |
| tree | 991a75afe9b009486a57834fefee075ec695a28c /passes/fsm/fsm_extract.cc | |
| parent | 5826670009e1018734de49aaf1554cb8a43d09d7 (diff) | |
| download | yosys-2bec47a4045d23d46e7d300cbf80b2dce1a549a9.tar.gz yosys-2bec47a4045d23d46e7d300cbf80b2dce1a549a9.tar.bz2 yosys-2bec47a4045d23d46e7d300cbf80b2dce1a549a9.zip | |
Use only module->addCell() and module->remove() to create and delete cells
Diffstat (limited to 'passes/fsm/fsm_extract.cc')
| -rw-r--r-- | passes/fsm/fsm_extract.cc | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index dfd025a51..1b5ea1bc0 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -270,9 +270,7 @@ static void extract_fsm(RTLIL::Wire *wire) // create fsm cell - RTLIL::Cell *fsm_cell = new RTLIL::Cell; - fsm_cell->name = stringf("$fsm$%s$%d", wire->name.c_str(), RTLIL::autoidx++); - fsm_cell->type = "$fsm"; + RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), RTLIL::autoidx++), "$fsm"); fsm_cell->connections["\\CLK"] = clk; fsm_cell->connections["\\ARST"] = arst; fsm_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity ? 1 : 0, 1); @@ -282,7 +280,6 @@ static void extract_fsm(RTLIL::Wire *wire) fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name); fsm_cell->attributes = wire->attributes; fsm_data.copy_to_cell(fsm_cell); - module->cells[fsm_cell->name] = fsm_cell; // rename original state wire |