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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 10:18:00 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 11:18:30 +0200 |
| commit | 10e5791c5e5660cb784503d36439ee90d61eb06b (patch) | |
| tree | d7bd3d8f1d0254e14fcf68ce25545f42afab9724 /passes/fsm/fsm_extract.cc | |
| parent | d088854b47f5f77c6a62be2ba4b895164938d7a2 (diff) | |
| download | yosys-10e5791c5e5660cb784503d36439ee90d61eb06b.tar.gz yosys-10e5791c5e5660cb784503d36439ee90d61eb06b.tar.bz2 yosys-10e5791c5e5660cb784503d36439ee90d61eb06b.zip | |
Refactoring: Renamed RTLIL::Design::modules to modules_
Diffstat (limited to 'passes/fsm/fsm_extract.cc')
| -rw-r--r-- | passes/fsm/fsm_extract.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 64b01064a..99352b10a 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -330,7 +330,7 @@ struct FsmExtractPass : public Pass { ct.setup_stdcells(); ct.setup_stdcells_mem(); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; |