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authorJim Lawson <ucbjrl@berkeley.edu>2018-08-22 08:42:34 -0700
committerGitHub <noreply@github.com>2018-08-22 08:42:34 -0700
commit2c0601eb6f2c5ed0d376ed880efda48a2aeeb9ef (patch)
tree02b9412c9249cce3714972c8385d66f8093bfc17 /passes/fsm/fsm_expand.cc
parent8b92ddb9d2635c30636b17ff3d24bc09a44b8551 (diff)
parent408077769ff022f78f10ec1ffb60926361f8dc9f (diff)
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Merge pull request #1 from YosysHQ/master
merge with YosysHQ master
Diffstat (limited to 'passes/fsm/fsm_expand.cc')
-rw-r--r--passes/fsm/fsm_expand.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc
index 2c344a1c1..c34d0c15c 100644
--- a/passes/fsm/fsm_expand.cc
+++ b/passes/fsm/fsm_expand.cc
@@ -265,7 +265,7 @@ struct FsmExpand
struct FsmExpandPass : public Pass {
FsmExpandPass() : Pass("fsm_expand", "expand FSM cells by merging logic into it") { }
- virtual void help()
+ void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -279,7 +279,7 @@ struct FsmExpandPass : public Pass {
log("word-wide cells. Call with -full to consider all cells for merging.\n");
log("\n");
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
bool full_mode = false;