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author | Clifford Wolf <clifford@clifford.at> | 2013-02-27 23:19:30 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-02-27 23:19:30 +0100 |
commit | 500786af5584c8a27e75bdf26f123328d9d574bd (patch) | |
tree | 865d5fcefcfbe522f2d81b784ef7e5aabe50bc8d /passes/extract | |
parent | 1bbc2b34c8c23f0da2d72f08c5cfb9dffa7fa673 (diff) | |
download | yosys-500786af5584c8a27e75bdf26f123328d9d574bd.tar.gz yosys-500786af5584c8a27e75bdf26f123328d9d574bd.tar.bz2 yosys-500786af5584c8a27e75bdf26f123328d9d574bd.zip |
Fixed "extract" pass for non-optimized needles
Diffstat (limited to 'passes/extract')
-rw-r--r-- | passes/extract/extract.cc | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/passes/extract/extract.cc b/passes/extract/extract.cc index 7541b2603..9b5991bfe 100644 --- a/passes/extract/extract.cc +++ b/passes/extract/extract.cc @@ -158,18 +158,17 @@ namespace RTLIL::Cell *needle_cell = (RTLIL::Cell*)mapping.needleUserData; RTLIL::Cell *haystack_cell = (RTLIL::Cell*)mapping.haystackUserData; - for (auto &conn : needle_cell->connections) - if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(conn.second)) - { - RTLIL::SigSpec sig = sigmap(conn.second); + for (auto &conn : needle_cell->connections) { + RTLIL::SigSpec sig = sigmap(conn.second); + if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) { sig.expand(); - for (int i = 0; i < sig.width; i++) for (auto &port : sig2port.find(sig.chunks[i])) { RTLIL::SigSpec bitsig = haystack_cell->connections.at(mapping.portMapping[conn.first]).extract(i, 1); cell->connections.at(port.first).replace(port.second, bitsig); } } + } haystack->cells.erase(haystack_cell->name); delete haystack_cell; |