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| author | Claire Xenia Wolf <claire@clairexen.net> | 2021-05-04 18:54:10 +0200 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2022-10-07 16:04:51 +0200 |
| commit | afa5e6bb53f15abf26ec9a0c633539cc95f57f60 (patch) | |
| tree | 406c2f429a801e62d210f90b820b2cc6cf14c60f /passes/equiv | |
| parent | 381ce66f5870291fe950c276c492b303f714738f (diff) | |
| download | yosys-afa5e6bb53f15abf26ec9a0c633539cc95f57f60.tar.gz yosys-afa5e6bb53f15abf26ec9a0c633539cc95f57f60.tar.bz2 yosys-afa5e6bb53f15abf26ec9a0c633539cc95f57f60.zip | |
Exclude primary inputs from quiv_make rewiring
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
Diffstat (limited to 'passes/equiv')
| -rw-r--r-- | passes/equiv/equiv_make.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index 4d9e3b71a..27cec7549 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -137,6 +137,7 @@ struct EquivMakeWorker { SigMap assign_map(equiv_mod); SigMap rd_signal_map; + SigPool primary_inputs; // list of cells without added $equiv cells auto cells_list = equiv_mod->cells().to_vector(); @@ -252,6 +253,9 @@ struct EquivMakeWorker gate_wire->port_input = false; equiv_mod->connect(gold_wire, wire); equiv_mod->connect(gate_wire, wire); + primary_inputs.add(assign_map(gold_wire)); + primary_inputs.add(assign_map(gate_wire)); + primary_inputs.add(wire); } else { @@ -283,6 +287,9 @@ struct EquivMakeWorker if (!ct.cell_output(c->type, conn.first)) { SigSpec old_sig = assign_map(conn.second); SigSpec new_sig = rd_signal_map(old_sig); + for (int i = 0; i < GetSize(old_sig); i++) + if (primary_inputs.check(old_sig[i])) + new_sig[i] = old_sig[i]; if (old_sig != new_sig) { log("Changing input %s of cell %s (%s): %s -> %s\n", log_id(conn.first), log_id(c), log_id(c->type), |