kernel: big fat patch to use more ID::*, otherwise ID(*)

10 files changed, 29 insertions, 29 deletions

diff --git a/passes/equiv/equiv_add.cc b/passes/equiv/equiv_add.cc
index 71599f46e..cdc74b0b2 100644
--- a/passes/equiv/equiv_add.cc
+++ b/passes/equiv/equiv_add.cc
@@ -152,7 +152,7 @@ struct EquivAddPass : public Pass {
 
 			for (int i = 0; i < GetSize(gold_signal); i++) {
 				Cell *equiv_cell = module->addEquiv(NEW_ID, gold_signal[i], gate_signal[i], equiv_signal[i]);
-				equiv_cell->set_bool_attribute("\\keep");
+				equiv_cell->set_bool_attribute(ID::keep);
 				to_equiv_bits[gold_signal[i]] = equiv_signal[i];
 				to_equiv_bits[gate_signal[i]] = equiv_signal[i];
 				added_equiv_cells.insert(equiv_cell);
diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc
index 77eec7490..ec651193e 100644
--- a/passes/equiv/equiv_induct.cc
+++ b/passes/equiv/equiv_induct.cc
@@ -58,7 +58,7 @@ struct EquivInductWorker
 				log_warning("No SAT model available for cell %s (%s).\n", log_id(cell), log_id(cell->type));
 				cell_warn_cache.insert(cell);
 			}
-			if (cell->type == "$equiv") {
+			if (cell->type == ID($equiv)) {
 				SigBit bit_a = sigmap(cell->getPort(ID::A)).as_bit();
 				SigBit bit_b = sigmap(cell->getPort(ID::B)).as_bit();
 				if (bit_a != bit_b) {
@@ -219,7 +219,7 @@ struct EquivInductPass : public Pass {
 			pool<Cell*> unproven_equiv_cells;
 
 			for (auto cell : module->selected_cells())
-				if (cell->type == "$equiv") {
+				if (cell->type == ID($equiv)) {
 					if (cell->getPort(ID::A) != cell->getPort(ID::B))
 						unproven_equiv_cells.insert(cell);
 				}
diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index 4855ce29e..50572ae5c 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -406,7 +406,7 @@ struct EquivMakeWorker
 	void init_bit2driven()
 	{
 		for (auto cell : equiv_mod->cells()) {
-			if (!ct.cell_known(cell->type) && !cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_", "$ff", "$_FF_"))
+			if (!ct.cell_known(cell->type) && !cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_)))
 				continue;
 			for (auto &conn : cell->connections())
 			{
diff --git a/passes/equiv/equiv_mark.cc b/passes/equiv/equiv_mark.cc
index b4d1d7871..737de25d9 100644
--- a/passes/equiv/equiv_mark.cc
+++ b/passes/equiv/equiv_mark.cc
@@ -48,7 +48,7 @@ struct EquivMarkWorker
 	{
 		for (auto cell : module->cells())
 		{
-			if (cell->type == "$equiv")
+			if (cell->type == ID($equiv))
 				equiv_cells.insert(cell->name);
 
 			for (auto &port : cell->connections())
@@ -139,7 +139,7 @@ struct EquivMarkWorker
 
 		for (auto cell : module->cells())
 		{
-			if (cell_regions.count(cell->name) || cell->type != "$equiv")
+			if (cell_regions.count(cell->name) || cell->type != ID($equiv))
 				continue;
 
 			SigSpec sig_a = sigmap(cell->getPort(ID::A));
@@ -176,10 +176,10 @@ struct EquivMarkWorker
 		{
 			if (cell_regions.count(cell->name)) {
 				int r = final_region_map.at(cell_regions.at(cell->name));
-				cell->attributes["\\equiv_region"] = Const(r);
+				cell->attributes[ID::equiv_region] = Const(r);
 				region_cell_count[r]++;
 			} else
-				cell->attributes.erase("\\equiv_region");
+				cell->attributes.erase(ID::equiv_region);
 		}
 
 		for (auto wire : module->wires())
@@ -191,10 +191,10 @@ struct EquivMarkWorker
 
 			if (GetSize(regions) == 1) {
 				int r = final_region_map.at(*regions.begin());
-				wire->attributes["\\equiv_region"] = Const(r);
+				wire->attributes[ID::equiv_region] = Const(r);
 				region_wire_count[r]++;
 			} else
-				wire->attributes.erase("\\equiv_region");
+				wire->attributes.erase(ID::equiv_region);
 		}
 
 		for (int i = 0; i < next_final_region; i++)
diff --git a/passes/equiv/equiv_miter.cc b/passes/equiv/equiv_miter.cc
index 5fd7c5418..085970189 100644
--- a/passes/equiv/equiv_miter.cc
+++ b/passes/equiv/equiv_miter.cc
@@ -47,7 +47,7 @@ struct EquivMiterWorker
 		if (cone.count(c))
 			return;
 
-		if (c->type == "$equiv" && !seed_cells.count(c)) {
+		if (c->type == ID($equiv) && !seed_cells.count(c)) {
 			leaves.insert(c);
 			return;
 		}
@@ -57,7 +57,7 @@ struct EquivMiterWorker
 		for (auto &conn : c->connections()) {
 			if (!ct.cell_input(c->type, conn.first))
 				continue;
-			if (c->type == "$equiv" && (conn.first == ID::A) != gold_mode)
+			if (c->type == ID($equiv) && (conn.first == ID::A) != gold_mode)
 				continue;
 			for (auto bit : sigmap(conn.second))
 				if (bit_to_driver.count(bit))
@@ -81,7 +81,7 @@ struct EquivMiterWorker
 		// find seed cells
 
 		for (auto c : source_module->selected_cells())
-			if (c->type == "$equiv") {
+			if (c->type == ID($equiv)) {
 				log("Seed $equiv cell: %s\n", log_id(c));
 				seed_cells.insert(c);
 			}
@@ -213,7 +213,7 @@ struct EquivMiterWorker
 		vector<Cell*> equiv_cells;
 
 		for (auto c : miter_module->cells())
-			if (c->type == "$equiv" && c->getPort(ID::A) != c->getPort(ID::B))
+			if (c->type == ID($equiv) && c->getPort(ID::A) != c->getPort(ID::B))
 				equiv_cells.push_back(c);
 
 		for (auto c : equiv_cells)
@@ -224,7 +224,7 @@ struct EquivMiterWorker
 					miter_module->Eq(NEW_ID, c->getPort(ID::A), c->getPort(ID::B));
 
 			if (mode_cmp) {
-				string cmp_name = string("\\cmp") + log_signal(c->getPort(ID::Y));
+				string cmp_name = stringf("\\cmp%s", log_signal(c->getPort(ID::Y)));
 				for (int i = 1; i < GetSize(cmp_name); i++)
 					if (cmp_name[i] == '\\')
 						cmp_name[i] = '_';
@@ -242,7 +242,7 @@ struct EquivMiterWorker
 		}
 
 		if (mode_trigger) {
-			auto w = miter_module->addWire("\\trigger");
+			auto w = miter_module->addWire(ID(trigger));
 			w->port_output = true;
 			miter_module->addReduceOr(NEW_ID, trigger_signals, w);
 		}
diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc
index 2a339682a..688c20f43 100644
--- a/passes/equiv/equiv_purge.cc
+++ b/passes/equiv/equiv_purge.cc
@@ -102,7 +102,7 @@ struct EquivPurgeWorker
 
 		for (auto cell : module->cells())
 		{
-			if (cell->type != "$equiv") {
+			if (cell->type != ID($equiv)) {
 				for (auto &port : cell->connections()) {
 					if (cell->input(port.first))
 						for (auto bit : sigmap(port.second))
@@ -167,7 +167,7 @@ struct EquivPurgeWorker
 				rewrite_sigmap.add(chunk, make_input(chunk));
 
 		for (auto cell : module->cells())
-			if (cell->type == "$equiv")
+			if (cell->type == ID($equiv))
 				cell->setPort(ID::Y, rewrite_sigmap(sigmap(cell->getPort(ID::Y))));
 
 		module->fixup_ports();
diff --git a/passes/equiv/equiv_remove.cc b/passes/equiv/equiv_remove.cc
index 2a78e5246..6daa112b5 100644
--- a/passes/equiv/equiv_remove.cc
+++ b/passes/equiv/equiv_remove.cc
@@ -68,7 +68,7 @@ struct EquivRemovePass : public Pass {
 		for (auto module : design->selected_modules())
 		{
 			for (auto cell : module->selected_cells())
-				if (cell->type == "$equiv" && (mode_gold || mode_gate || cell->getPort(ID::A) == cell->getPort(ID::B))) {
+				if (cell->type == ID($equiv) && (mode_gold || mode_gate || cell->getPort(ID::A) == cell->getPort(ID::B))) {
 					log("Removing $equiv cell %s.%s (%s).\n", log_id(module), log_id(cell), log_signal(cell->getPort(ID::Y)));
 					module->connect(cell->getPort(ID::Y), mode_gate ? cell->getPort(ID::B) : cell->getPort(ID::A));
 					module->remove(cell);
diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc
index 0e5348880..4d2839f4d 100644
--- a/passes/equiv/equiv_simple.cc
+++ b/passes/equiv/equiv_simple.cc
@@ -60,8 +60,8 @@ struct EquivSimpleWorker
 		for (auto &conn : cell->connections())
 			if (yosys_celltypes.cell_input(cell->type, conn.first))
 				for (auto bit : sigmap(conn.second)) {
-					if (cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_", "$ff", "$_FF_")) {
-						if (!conn.first.in("\\CLK", "\\C"))
+					if (cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_))) {
+						if (!conn.first.in(ID::CLK, ID::C))
 							next_seed.insert(bit);
 					} else
 						find_input_cone(next_seed, cells_cone, bits_cone, cells_stop, bits_stop, input_bits, bit);
@@ -344,7 +344,7 @@ struct EquivSimplePass : public Pass {
 			int unproven_cells_counter = 0;
 
 			for (auto cell : module->selected_cells())
-				if (cell->type == "$equiv" && cell->getPort(ID::A) != cell->getPort(ID::B)) {
+				if (cell->type == ID($equiv) && cell->getPort(ID::A) != cell->getPort(ID::B)) {
 					auto bit = sigmap(cell->getPort(ID::Y).as_bit());
 					auto bit_group = bit;
 					if (!nogroup && bit_group.wire)
@@ -360,7 +360,7 @@ struct EquivSimplePass : public Pass {
 					unproven_cells_counter, GetSize(unproven_equiv_cells), log_id(module));
 
 			for (auto cell : module->cells()) {
-				if (!ct.cell_known(cell->type) && !cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_", "$ff", "$_FF_"))
+				if (!ct.cell_known(cell->type) && !cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_)))
 					continue;
 				for (auto &conn : cell->connections())
 					if (yosys_celltypes.cell_output(cell->type, conn.first))
diff --git a/passes/equiv/equiv_status.cc b/passes/equiv/equiv_status.cc
index ac3af59f6..258e2e45b 100644
--- a/passes/equiv/equiv_status.cc
+++ b/passes/equiv/equiv_status.cc
@@ -59,7 +59,7 @@ struct EquivStatusPass : public Pass {
 			int proven_equiv_cells = 0;
 
 			for (auto cell : module->selected_cells())
-				if (cell->type == "$equiv") {
+				if (cell->type == ID($equiv)) {
 					if (cell->getPort(ID::A) != cell->getPort(ID::B))
 						unproven_equiv_cells.push_back(cell);
 					else
diff --git a/passes/equiv/equiv_struct.cc b/passes/equiv/equiv_struct.cc
index ba1fd1d26..1b7bf96a8 100644
--- a/passes/equiv/equiv_struct.cc
+++ b/passes/equiv/equiv_struct.cc
@@ -110,9 +110,9 @@ struct EquivStructWorker
 			module->connect(sig_b, sig_a);
 		}
 
-		auto merged_attr = cell_b->get_strpool_attribute("\\equiv_merged");
+		auto merged_attr = cell_b->get_strpool_attribute(ID::equiv_merged);
 		merged_attr.insert(log_id(cell_b));
-		cell_a->add_strpool_attribute("\\equiv_merged", merged_attr);
+		cell_a->add_strpool_attribute(ID::equiv_merged, merged_attr);
 		module->remove(cell_b);
 	}
 
@@ -126,7 +126,7 @@ struct EquivStructWorker
 		pool<IdString> cells;
 
 		for (auto cell : module->selected_cells())
-			if (cell->type == "$equiv") {
+			if (cell->type == ID($equiv)) {
 				SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit());
 				SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit());
 				equiv_bits.add(sig_b, sig_a);
@@ -139,7 +139,7 @@ struct EquivStructWorker
 			}
 
 		for (auto cell : module->selected_cells())
-			if (cell->type == "$equiv") {
+			if (cell->type == ID($equiv)) {
 				SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit());
 				SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit());
 				SigBit sig_y = sigmap(cell->getPort(ID::Y).as_bit());
@@ -316,7 +316,7 @@ struct EquivStructPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
 	{
-		pool<IdString> fwonly_cells({ "$equiv" });
+		pool<IdString> fwonly_cells({ ID($equiv) });
 		bool mode_icells = false;
 		bool mode_fwd = false;
 		int max_iter = -1;