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| author | Clifford Wolf <clifford@clifford.at> | 2015-10-25 19:30:49 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-10-25 19:30:49 +0100 |
| commit | 207736b4ee0363ff6714071e64024965916eafc2 (patch) | |
| tree | 31092cfab4323500bc491d8b59deee9e297730d0 /passes/equiv | |
| parent | da923c198e770806a4abb749acc75fa337247920 (diff) | |
| download | yosys-207736b4ee0363ff6714071e64024965916eafc2.tar.gz yosys-207736b4ee0363ff6714071e64024965916eafc2.tar.bz2 yosys-207736b4ee0363ff6714071e64024965916eafc2.zip | |
Import more std:: stuff into Yosys namespace
Diffstat (limited to 'passes/equiv')
| -rw-r--r-- | passes/equiv/equiv_add.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/equiv/equiv_add.cc b/passes/equiv/equiv_add.cc index 7b8ba9058..9ae490fe7 100644 --- a/passes/equiv/equiv_add.cc +++ b/passes/equiv/equiv_add.cc @@ -63,7 +63,7 @@ struct EquivAddPass : public Pass { auto port = conn.first; SigSpec gold_sig = gold_cell->getPort(port); SigSpec gate_sig = gate_cell->getPort(port); - int width = std::min(GetSize(gold_sig), GetSize(gate_sig)); + int width = min(GetSize(gold_sig), GetSize(gate_sig)); if (gold_cell->input(port) && gate_cell->input(port)) { |