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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 07:13:33 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-02 07:13:33 -0700 |
| commit | 37f42fe102e329793b884a47321423062eedfce7 (patch) | |
| tree | 42cca1494ce7d806e8a638fe56bc8acd13733a21 /passes/cmds | |
| parent | 347774945972dc71910a3e38c9ec678f74f97d03 (diff) | |
| parent | 348e8923148f1cc1bfb87bb71b7566d4bc111704 (diff) | |
| download | yosys-37f42fe102e329793b884a47321423062eedfce7.tar.gz yosys-37f42fe102e329793b884a47321423062eedfce7.tar.bz2 yosys-37f42fe102e329793b884a47321423062eedfce7.zip | |
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup
kernel: speedup by using more pass-by-const-ref
Diffstat (limited to 'passes/cmds')
| -rw-r--r-- | passes/cmds/trace.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/trace.cc b/passes/cmds/trace.cc index cf3e46ace..8446e27b3 100644 --- a/passes/cmds/trace.cc +++ b/passes/cmds/trace.cc @@ -35,7 +35,7 @@ struct TraceMonitor : public RTLIL::Monitor log("#TRACE# Module delete: %s\n", log_id(module)); } - void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE + void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) YS_OVERRIDE { log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig)); } |