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author | Clifford Wolf <clifford@clifford.at> | 2014-08-02 13:11:01 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-08-02 13:19:57 +0200 |
commit | b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3 (patch) | |
tree | fa56668843c23b8d03a0652be802410f888c6384 /passes/cmds/splice.cc | |
parent | 14412e6c957a34381c33740426b35f7b90a446be (diff) | |
download | yosys-b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3.tar.gz yosys-b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3.tar.bz2 yosys-b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3.zip |
More cleanups related to RTLIL::IdString usage
Diffstat (limited to 'passes/cmds/splice.cc')
-rw-r--r-- | passes/cmds/splice.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 07c6150cc..ca71f7d8d 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -33,8 +33,8 @@ struct SpliceWorker bool sel_by_wire; bool sel_any_bit; bool no_outputs; - std::set<std::string> ports; - std::set<std::string> no_ports; + std::set<RTLIL::IdString> ports; + std::set<RTLIL::IdString> no_ports; CellTypes ct; SigMap sigmap; @@ -224,7 +224,7 @@ struct SpliceWorker for (auto &it : rework_wires) { - std::string orig_name = it.first->name; + RTLIL::IdString orig_name = it.first->name; module->rename(it.first, NEW_ID); RTLIL::Wire *new_port = module->addWire(orig_name, it.first); @@ -283,7 +283,7 @@ struct SplicePass : public Pass { bool sel_by_wire = false; bool sel_any_bit = false; bool no_outputs = false; - std::set<std::string> ports, no_ports; + std::set<RTLIL::IdString> ports, no_ports; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { |