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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-20 20:51:54 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-20 20:51:54 +0200 |
| commit | f84a84e3f1a27b361c21fcd30fcf50c1a6586629 (patch) | |
| tree | 2d6b8acf72eead2e314295326d567e17e0c66871 /passes/cmds/show.cc | |
| parent | e3687f6f4e10789223213949b8490bd83ec285f2 (diff) | |
| parent | f3ad8d680a3195ab9525b0a8b3f8dbff9d5e6e24 (diff) | |
| download | yosys-f84a84e3f1a27b361c21fcd30fcf50c1a6586629.tar.gz yosys-f84a84e3f1a27b361c21fcd30fcf50c1a6586629.tar.bz2 yosys-f84a84e3f1a27b361c21fcd30fcf50c1a6586629.zip | |
Merge pull request #943 from YosysHQ/clifford/whitebox
[WIP] Add "whitebox" attribute, add "read_verilog -wb"
Diffstat (limited to 'passes/cmds/show.cc')
| -rw-r--r-- | passes/cmds/show.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 0eadd904a..cf729215f 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -574,7 +574,7 @@ struct ShowWorker if (!design->selected_module(module->name)) continue; if (design->selected_whole_module(module->name)) { - if (module->get_bool_attribute("\\blackbox")) { + if (module->get_blackbox_attribute()) { // log("Skipping blackbox module %s.\n", id2cstr(module->name)); continue; } else @@ -790,7 +790,7 @@ struct ShowPass : public Pass { if (format != "ps" && format != "dot") { int modcount = 0; for (auto &mod_it : design->modules_) { - if (mod_it.second->get_bool_attribute("\\blackbox")) + if (mod_it.second->get_blackbox_attribute()) continue; if (mod_it.second->cells_.empty() && mod_it.second->connections().empty()) continue; |