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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-13 09:49:15 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-13 09:49:15 -0700 |
| commit | 95e80809a5801743fabb2836fa25f3c3732a9a24 (patch) | |
| tree | e0ba8897072f7ffe7fa9bf3ac6a958efbc5c83bc /passes/cmds/scc.cc | |
| parent | c487a8ff25a89506423e868ff3b4345bc36a8e00 (diff) | |
| download | yosys-95e80809a5801743fabb2836fa25f3c3732a9a24.tar.gz yosys-95e80809a5801743fabb2836fa25f3c3732a9a24.tar.bz2 yosys-95e80809a5801743fabb2836fa25f3c3732a9a24.zip | |
Revert "SigSet<Cell*> to use stable compare class"
This reverts commit 4ea34aaacdf6f76e11a83d5eb2a53ba7e75f7c11.
Diffstat (limited to 'passes/cmds/scc.cc')
| -rw-r--r-- | passes/cmds/scc.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 0a4f9e98d..99f4fbae8 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -116,7 +116,7 @@ struct SccWorker } SigPool selectedSignals; - SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> sigToNextCells; + SigSet<RTLIL::Cell*> sigToNextCells; for (auto &it : module->wires_) if (design->selected(module, it.second)) |