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author | whitequark <whitequark@whitequark.org> | 2020-06-19 06:15:33 +0000 |
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committer | GitHub <noreply@github.com> | 2020-06-19 06:15:33 +0000 |
commit | ede4b10da8fdbdcff900b93c6c723516901483ff (patch) | |
tree | d949c995f56d6c07dfe7d18ca46547a3296079b6 /passes/cmds/rename.cc | |
parent | bcbd44c673e07c44da735ef1d7f6eb2b6c328f98 (diff) | |
parent | 60478a8e3a7b929ea7e4f4cd1b538b41ca1f34bb (diff) | |
download | yosys-ede4b10da8fdbdcff900b93c6c723516901483ff.tar.gz yosys-ede4b10da8fdbdcff900b93c6c723516901483ff.tar.bz2 yosys-ede4b10da8fdbdcff900b93c6c723516901483ff.zip |
Merge pull request #2173 from whitequark/use-cxx11-final-override
Use C++11 final/override/[[noreturn]]
Diffstat (limited to 'passes/cmds/rename.cc')
-rw-r--r-- | passes/cmds/rename.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index 7d6d84d42..6326b4b15 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -104,7 +104,7 @@ static IdString derive_name_from_cell_output_wire(const RTLIL::Cell *cell) struct RenamePass : public Pass { RenamePass() : Pass("rename", "rename object in the design") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -152,7 +152,7 @@ struct RenamePass : public Pass { log("Rename top module.\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { std::string pattern_prefix = "_", pattern_suffix = "_"; bool flag_src = false; |