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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-12 12:57:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 07:14:08 -0700 |
| commit | fdafb74eb77e33e9fa2b4e591804d1d02c122ff9 (patch) | |
| tree | 49cd4fc4493b1ecfcf50aabda00aee1130124fa3 /passes/cmds/design.cc | |
| parent | 164dd0f6b298e416bd1ef882f21a4d0b5acfd039 (diff) | |
| download | yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.tar.gz yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.tar.bz2 yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.zip | |
kernel: use more ID::*
Diffstat (limited to 'passes/cmds/design.cc')
| -rw-r--r-- | passes/cmds/design.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 7ea0be9ee..4fd43329f 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -207,7 +207,7 @@ struct DesignPass : public Pass { if (import_mode) { for (auto module : copy_src_modules) { - if (module->get_bool_attribute("\\top")) { + if (module->get_bool_attribute(ID::top)) { copy_src_modules.clear(); copy_src_modules.push_back(module); break; @@ -244,7 +244,7 @@ struct DesignPass : public Pass { RTLIL::Module *t = mod->clone(); t->name = prefix; t->design = copy_to_design; - t->attributes.erase("\\top"); + t->attributes.erase(ID::top); copy_to_design->add(t); queue.insert(t); @@ -276,7 +276,7 @@ struct DesignPass : public Pass { RTLIL::Module *t = fmod->clone(); t->name = trg_name; t->design = copy_to_design; - t->attributes.erase("\\top"); + t->attributes.erase(ID::top); copy_to_design->add(t); queue.insert(t); |