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| author | Jim Lawson <ucbjrl@berkeley.edu> | 2018-08-22 08:42:34 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-08-22 08:42:34 -0700 |
| commit | 2c0601eb6f2c5ed0d376ed880efda48a2aeeb9ef (patch) | |
| tree | 02b9412c9249cce3714972c8385d66f8093bfc17 /passes/cmds/design.cc | |
| parent | 8b92ddb9d2635c30636b17ff3d24bc09a44b8551 (diff) | |
| parent | 408077769ff022f78f10ec1ffb60926361f8dc9f (diff) | |
| download | yosys-2c0601eb6f2c5ed0d376ed880efda48a2aeeb9ef.tar.gz yosys-2c0601eb6f2c5ed0d376ed880efda48a2aeeb9ef.tar.bz2 yosys-2c0601eb6f2c5ed0d376ed880efda48a2aeeb9ef.zip | |
Merge pull request #1 from YosysHQ/master
merge with YosysHQ master
Diffstat (limited to 'passes/cmds/design.cc')
| -rw-r--r-- | passes/cmds/design.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 490c8dde5..172addcc1 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -27,7 +27,7 @@ std::vector<RTLIL::Design*> pushed_designs; struct DesignPass : public Pass { DesignPass() : Pass("design", "save, restore and reset current design") { } - virtual ~DesignPass() { + ~DesignPass() YS_OVERRIDE { for (auto &it : saved_designs) delete it.second; saved_designs.clear(); @@ -35,7 +35,7 @@ struct DesignPass : public Pass { delete it; pushed_designs.clear(); } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -94,7 +94,7 @@ struct DesignPass : public Pass { log("between calls to 'read_verilog'. This command resets this memory.\n"); log("\n"); } - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { bool got_mode = false; bool reset_mode = false; |