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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-02 00:45:25 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-02 00:45:25 +0200 |
| commit | 14412e6c957a34381c33740426b35f7b90a446be (patch) | |
| tree | d45765adc9aa28301ab0c9d100728a5d720503fd /passes/cmds/design.cc | |
| parent | 75ffd1643c97321255bc591edf0c1a7097b8dce9 (diff) | |
| download | yosys-14412e6c957a34381c33740426b35f7b90a446be.tar.gz yosys-14412e6c957a34381c33740426b35f7b90a446be.tar.bz2 yosys-14412e6c957a34381c33740426b35f7b90a446be.zip | |
Preparations for RTLIL::IdString redesign: cleanup of existing code
Diffstat (limited to 'passes/cmds/design.cc')
| -rw-r--r-- | passes/cmds/design.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 41548f621..260e7b5d9 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -192,7 +192,7 @@ struct DesignPass : public Pass { for (auto mod : copy_src_modules) { - std::string trg_name = as_name.empty() ? mod->name : RTLIL::escape_id(as_name); + std::string trg_name = as_name.empty() ? std::string(mod->name) : RTLIL::escape_id(as_name); if (copy_to_design->modules_.count(trg_name)) delete copy_to_design->modules_.at(trg_name); |