Changed a lot of code to the new RTLIL::Wire constructors

1 files changed, 5 insertions, 30 deletions

diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc
index 79b7c3c30..df5a3d4b9 100644
--- a/passes/cmds/delete.cc
+++ b/passes/cmds/delete.cc
@@ -21,22 +21,6 @@
 #include "kernel/rtlil.h"
 #include "kernel/log.h"
 
-struct DeleteWireWorker
-{
-	RTLIL::Module *module;
-	std::set<std::string> *delete_wires_p;
-
-	void operator()(RTLIL::SigSpec &sig) {
-		std::vector<RTLIL::SigChunk> chunks = sig;
-		for (auto &c : chunks)
-			if (c.wire != NULL && delete_wires_p->count(c.wire->name)) {
-				c.wire = module->addWire(NEW_ID, c.width);
-				c.offset = 0;
-			}
-		sig = chunks;
-	}
-};
-
 struct DeletePass : public Pass {
 	DeletePass() : Pass("delete", "delete objects in the design") { }
 	virtual void help()
@@ -106,14 +90,14 @@ struct DeletePass : public Pass {
 				continue;
 			}
 
-			std::set<std::string> delete_wires;
+			std::set<RTLIL::Wire*> delete_wires;
 			std::set<RTLIL::Cell*> delete_cells;
 			std::set<std::string> delete_procs;
 			std::set<std::string> delete_mems;
 
 			for (auto &it : module->wires)
 				if (design->selected(module, it.second))
-					delete_wires.insert(it.first);
+					delete_wires.insert(it.second);
 
 			for (auto &it : module->memories)
 				if (design->selected(module, it.second))
@@ -131,30 +115,21 @@ struct DeletePass : public Pass {
 				if (design->selected(module, it.second))
 					delete_procs.insert(it.first);
 
-			DeleteWireWorker delete_wire_worker;
-			delete_wire_worker.module = module;
-			delete_wire_worker.delete_wires_p = &delete_wires;
-			module->rewrite_sigspecs(delete_wire_worker);
-
-			for (auto &it : delete_wires) {
-				delete module->wires.at(it);
-				module->wires.erase(it);
-			}
-
 			for (auto &it : delete_mems) {
 				delete module->memories.at(it);
 				module->memories.erase(it);
 			}
 
-			for (auto &it : delete_cells) {
+			for (auto &it : delete_cells)
 				module->remove(it);
-			}
 
 			for (auto &it : delete_procs) {
 				delete module->processes.at(it);
 				module->processes.erase(it);
 			}
 
+			module->remove(delete_wires);
+
 			module->fixup_ports();
 		}