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| author | Udi Finkelstein <github@udifink.com> | 2018-09-18 01:27:01 +0300 |
|---|---|---|
| committer | Udi Finkelstein <github@udifink.com> | 2018-09-18 01:27:01 +0300 |
| commit | c693f595c53e2e40840ff40b5b5ba06767582d23 (patch) | |
| tree | de5e3f353f3222abca7186996e88cd9d635a964b /passes/cmds/connect.cc | |
| parent | f6fe73b31f6e6d8966ad4ddae860b4d79133cce2 (diff) | |
| parent | 592a82c0ad8beb6de023aa2a131aab6472f949e8 (diff) | |
| download | yosys-c693f595c53e2e40840ff40b5b5ba06767582d23.tar.gz yosys-c693f595c53e2e40840ff40b5b5ba06767582d23.tar.bz2 yosys-c693f595c53e2e40840ff40b5b5ba06767582d23.zip | |
Merge branch 'master' into pr_reg_wire_error
Diffstat (limited to 'passes/cmds/connect.cc')
| -rw-r--r-- | passes/cmds/connect.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index 52611cf44..d480b79ac 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -43,7 +43,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap & struct ConnectPass : public Pass { ConnectPass() : Pass("connect", "create or remove connections") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -75,7 +75,7 @@ struct ConnectPass : public Pass { log("This command does not operate on module with processes.\n"); log("\n"); } - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { RTLIL::Module *module = NULL; for (auto &it : design->modules_) { |