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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-20 20:51:54 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-20 20:51:54 +0200 |
| commit | f84a84e3f1a27b361c21fcd30fcf50c1a6586629 (patch) | |
| tree | 2d6b8acf72eead2e314295326d567e17e0c66871 /passes/cmds/add.cc | |
| parent | e3687f6f4e10789223213949b8490bd83ec285f2 (diff) | |
| parent | f3ad8d680a3195ab9525b0a8b3f8dbff9d5e6e24 (diff) | |
| download | yosys-f84a84e3f1a27b361c21fcd30fcf50c1a6586629.tar.gz yosys-f84a84e3f1a27b361c21fcd30fcf50c1a6586629.tar.bz2 yosys-f84a84e3f1a27b361c21fcd30fcf50c1a6586629.zip | |
Merge pull request #943 from YosysHQ/clifford/whitebox
[WIP] Add "whitebox" attribute, add "read_verilog -wb"
Diffstat (limited to 'passes/cmds/add.cc')
| -rw-r--r-- | passes/cmds/add.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index cfccca966..af6f7043d 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -71,7 +71,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n RTLIL::Module *mod = design->modules_.at(it.second->type); if (!design->selected_whole_module(mod->name)) continue; - if (mod->get_bool_attribute("\\blackbox")) + if (mod->get_blackbox_attribute()) continue; if (it.second->hasPort(name)) continue; |