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| author | Aman Goel <amangoel@umich.edu> | 2019-09-27 12:30:27 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-09-27 12:30:27 -0400 |
| commit | cb0dc6e68b9432edc9c30c153954be53c8576911 (patch) | |
| tree | c137f970f949117d04632158d73bfe1f9c146e6f /passes/cmds/add.cc | |
| parent | 4d343fc1cdafe469484846051680ca0b1f948549 (diff) | |
| parent | 4b15cf5f76e2226bbce1a73d1e0ff54fbf093fe8 (diff) | |
| download | yosys-cb0dc6e68b9432edc9c30c153954be53c8576911.tar.gz yosys-cb0dc6e68b9432edc9c30c153954be53c8576911.tar.bz2 yosys-cb0dc6e68b9432edc9c30c153954be53c8576911.zip | |
Merge pull request #7 from YosysHQ/master
Syncing with official repo
Diffstat (limited to 'passes/cmds/add.cc')
| -rw-r--r-- | passes/cmds/add.cc | 24 |
1 files changed, 21 insertions, 3 deletions
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index e698926f9..dd05ac81f 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -71,7 +71,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n RTLIL::Module *mod = design->modules_.at(it.second->type); if (!design->selected_whole_module(mod->name)) continue; - if (mod->get_bool_attribute("\\blackbox")) + if (mod->get_blackbox_attribute()) continue; if (it.second->hasPort(name)) continue; @@ -83,7 +83,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n struct AddPass : public Pass { AddPass() : Pass("add", "add objects to the design") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -105,14 +105,20 @@ struct AddPass : public Pass { log("Like 'add -input', but also connect the signal between instances of the\n"); log("selected modules.\n"); log("\n"); + log("\n"); + log(" add -mod <name[s]>\n"); + log("\n"); + log("Add module[s] with the specified name[s].\n"); + log("\n"); } - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { std::string command; std::string arg_name; bool arg_flag_input = false; bool arg_flag_output = false; bool arg_flag_global = false; + bool mod_mode = false; int arg_width = 0; size_t argidx; @@ -133,8 +139,20 @@ struct AddPass : public Pass { arg_width = atoi(args[++argidx].c_str()); continue; } + if (arg == "-mod") { + mod_mode = true; + argidx++; + break; + } break; } + + if (mod_mode) { + for (; argidx < args.size(); argidx++) + design->addModule(RTLIL::escape_id(args[argidx])); + return; + } + extra_args(args, argidx, design); for (auto &mod : design->modules_) |