diff options
| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-21 10:51:34 +0200 |
|---|---|---|
| committer | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-21 10:51:34 +0200 |
| commit | 69fb3b8db21c8a50fa333bff3ef844af42729e0d (patch) | |
| tree | 1a62aebe9ece22b19b4087f2c5cb5581b571c270 /passes/cmds/add.cc | |
| parent | 72323e11a4ee222c0ce928669d33333c46fb25aa (diff) | |
| parent | fa989e59e5a37d804d8a82050e022b8f4b7070d8 (diff) | |
| download | yosys-69fb3b8db21c8a50fa333bff3ef844af42729e0d.tar.gz yosys-69fb3b8db21c8a50fa333bff3ef844af42729e0d.tar.bz2 yosys-69fb3b8db21c8a50fa333bff3ef844af42729e0d.zip | |
Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin
Diffstat (limited to 'passes/cmds/add.cc')
| -rw-r--r-- | passes/cmds/add.cc | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index af6f7043d..dd05ac81f 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -105,6 +105,11 @@ struct AddPass : public Pass { log("Like 'add -input', but also connect the signal between instances of the\n"); log("selected modules.\n"); log("\n"); + log("\n"); + log(" add -mod <name[s]>\n"); + log("\n"); + log("Add module[s] with the specified name[s].\n"); + log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { @@ -113,6 +118,7 @@ struct AddPass : public Pass { bool arg_flag_input = false; bool arg_flag_output = false; bool arg_flag_global = false; + bool mod_mode = false; int arg_width = 0; size_t argidx; @@ -133,8 +139,20 @@ struct AddPass : public Pass { arg_width = atoi(args[++argidx].c_str()); continue; } + if (arg == "-mod") { + mod_mode = true; + argidx++; + break; + } break; } + + if (mod_mode) { + for (; argidx < args.size(); argidx++) + design->addModule(RTLIL::escape_id(args[argidx])); + return; + } + extra_args(args, argidx, design); for (auto &mod : design->modules_) |